Chipcraft 3.0 - 24 Hours Hackathon

24-Hour VLSI Physical Design Challenge

The 24-Hour VLSI Physical Design Challenge is an intensive hands-on technical event designed to provide participants with practical exposure to the complete ASIC design flow using industry-standard Synopsys EDA tools.

Participants will take a digital design concept from synthesizable RTL to physical layout, experiencing the major stages involved in modern VLSI chip implementation. The challenge begins with designing and developing a synthesizable RTL module, followed by functional verification through simulation to ensure that the design meets its intended specifications.

Once the RTL design is verified, participants will perform logic synthesis to convert the RTL description into a gate-level netlist. The synthesized design will then proceed through the physical design flow, including floorplanning, placement, clock and routing-related implementation steps, and routing, leading to the generation of the final physical layout.

Throughout the challenge, participants will gain valuable experience in understanding design constraints, timing considerations, area optimization, and the relationship between logical design and physical implementation.

Challenge Flow

- Design a synthesizable RTL module
- Perform functional verification through simulation
- Execute logic synthesis
- Generate and analyze the gate-level netlist
- Perform physical design implementation
- Carry out placement and routing
- Check design quality and implementation results
- Generate the final IC layout

The event aims to bridge the gap between academic learning and industry practice by providing participants with exposure to a realistic VLSI design workflow. Working within a 24-hour challenge format, participants will test their technical knowledge, problem-solving abilities, design optimization skills, and ability to work under time constraints.

By the end of the challenge, participants will have experienced a complete journey from RTL Design → Verification → Gate-Level Netlist → Physical Design → Placement & Routing → Final Layout, using Synopsys EDA tools.

Join the challenge and experience the journey of transforming digital logic into a physical chip layout!